Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension

ABSTRACT

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/684,122, filed Mar. 9, 2007.

BACKGROUND

The present invention related generally to the fabrication ofcomplementary metal oxide semiconductor (CMOS) field effect transistors(FET), and more particularly, to a method for forming ultra-thin SOI(UTSOI) field effect transistors with stressed channel regions whichprovide increased carrier mobility among other benefits.

CMOS FETs are employed in almost every electronic circuit applicationsuch as signal processing, computing, and wireless communications. Ithas been demonstrated that ultra-thin SOI (UTSOI) FETs have a very goodshort channel control due to extremely thin channel region. Thin bodydevices however, lead to high series resistance Rext, which can bemitigated by forming raised source/drain (RSD) regions. It has also beendemonstrated however, that thick channel SOI FETs exhibit improved FETperformance such as switching speed and drive current, by applyingstress in the channel. The improvement stems from enhanced carriermobility in stressed FET channels.

Incorporating stress into UTSOI FETs is a challenge because of the tinchannel region.

Commonly-owned, co-pending United States Patent Publication No. US20060175659A1 appears to describe a substrate having an UTSOI region and abulk-Si region, and, in particular, forming of nFET and pFET devices onUTSOI.

Commonly-owned, co-pending United States Patent Publication No.US20050093021A1 describes a strained SiGe layer epitaxially grown on theSi body serving as a buried channel for holes, a Si layer epitaxiallygrown on the SiGe layer serving as a surface channel for electrons, anda source and a drain containing an epitaxially deposited, strained SiGeof opposing conductivity type than the Si body.

Commonly-owned co-pending U.S. Pat. No. 6,939,751 describes a (RaisedSource Drain) RSD FET device with a recessed channel is formed with araised silicon sources and drains and a gate electrode structure formedon an SOI structure (a Si layer formed on a substrate).

None of this prior art however, addresses the integration of an embeddedpFET SiGe extension with raised source/drain regions.

It would thus be highly desirable to provide a method of making UTSOICMOS devices where the PFET has an embedded SiGe extensions region and,where both NFETs and PFETs have raised source/drain structures.

SUMMARY

The present invention provides a novel semiconductor device structurethat includes integrating embedded PFET devices with a SiGe extensionwith raised CMOS source drain regions. Particularly, according to theinvention, epitaxially grown raised source and drain structures areformed to reduce contact and source/drain resistance. Additionally,implemented are the embedded SiGe extensions to improve the PFET deviceextension and channel region conductivity.

The present invention provides a methodology that includes selectivelygrowing embedded SiGe (eSiGe) extensions in pFET regions and formingstrain-free raised Si or SiGe source/drain (RSD) regions on CMOS. TheeSiGe extension regions enhance hole mobility in the pFET channels andreduce resistance in the pFET extensions. The strain-free raisedsource/drain regions reduce contact resistance in both UTSOI pFETs andnFETs.

Thus, according to one aspect of the invention, there is provided anovel PFET transistor device comprising:

a semiconductor substrate having a buried layer of insulator materialformed therein and an Ultra-thin Silicon On Insulator (UTSOI) layerformed a top said buried layer of insulator material, said UTSOI layerproviding an active area for a PFET device;

a gate structure including a gate dielectric layer formed in said UTSOIactive area for said PFET device and a gate electrode conductor formedatop said gate dielectric layer;

epitaxially grown embedded semiconductor extensions formed in respectiverecesses created as a result of removing portions of the UTSOI layer atrespective source region and drain region at each side of said gatestructure of said PFET device; and,

raised source/drain (RSD) structures on top of respective epitaxiallygrown embedded semiconductor extensions,

wherein said epitaxially grown embedded semiconductor PFET extensionscreate compressive stress in the UTSOI layer thereby enhancing PFETdevice performance.

According to this aspect of the invention, a thickness of the UTSOIlayer ranges between 10 Å to about 300 Å. It is further understood thatan n-well structure is formed in the UTSOI regions for the PFET device.

Preferably, each of the formed RSD structures are distanced from a gateedge by a distance sufficient to lower parasitic capacitance between thegate and the respective source/drain. This distance may range between 30nm-40 nm distance corresponding to the thickness of formed thickdisposable sidewall spacers at sidewalls of said gate electrode prior toforming the raised RSD structures.

According to another aspect of the invention, there is provided a novelmethod of forming a PFET transistor device comprising:

a) forming an Ultra-thin Silicon On Insulator (UTSOI) layer a top aburied layer of insulator material within a semiconductor substrate,said UTSOI layer providing an active area for a PFET device;

b) forming atop said UTSOI active area a gate structure for said PFETdevice, said gate structure including a gate dielectric layer formedatop said UTSOI active layer and a corresponding gate conductor formedatop said gate dielectric layer;

c) removing portions of the UTSOI layer at respective source region anddrain region at each side of said gate electrode of said PFET device tocreate a respective recess at the active UTSOI area while leaving saidUTSOI layer under said gate electrode defining a gate channel region forthe PFET device;

d) epitaxially growing embedded semiconductor extensions in eachrespective recess corresponding to said source and drain regions of thePFET device; and

e) forming thick disposable sidewall spacers at sidewalls of said gateelectrode of said PFET device;

f) forming raised source/drain (RSD) structures on top of respectiveepitaxially grown embedded semiconductor extensions corresponding tosaid source and drain regions of the PFET device; and,

g) removing said thick disposable sidewall spacers at said PFET device,

wherein said epitaxially grown embedded semiconductor extensions createcompressive stress in the thin SOI layer thereby enhancing deviceperformance.

Preferably, each of the formed RSD structures are distanced from a gateedge by a distance sufficient to lower parasitic capacitance between thegate and the respective source/drain. This distance may range between 30nm-40 nm distance corresponding to the thickness of formed thickdisposable sidewall spacers at sidewalls of said gate electrode prior toforming the raised RSD structures.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present invention willbecome apparent to one skilled in the art, in view of the followingdetailed description taken in combination with the attached drawings, inwhich:

FIG. 1 depicts, through cross-sectional view, a resulting intermediatesemiconductor structure after applying processing steps for forming NFETgate electrode and PFET gate electrode structures fabricated on an SOIstructure including a buried oxide (BOX) region;

FIG. 2 illustrates, through cross-sectional view, a resultingintermediate semiconductor structure after applying processing steps forforming thin disposable spacers on each sidewall of the PFET gateelectrode and thin disposable cover on the entire NFET structure;

FIG. 3 depicts, through a cross-sectional view, a resulting intermediatesemiconductor structure after applying processing steps for creating arecess in the Si active region at the PFET device by removing portionsof the SOI layer;

FIG. 4 depicts, through a cross-sectional view, a resulting intermediatesemiconductor structure after applying processing steps for epitaxiallygrowing embedded SiGe extensions corresponding to drain and sourceregions for the PFET device;

FIG. 5 depicts, through a cross-sectional view, a resulting intermediatesemiconductor structure after performing an oxidation step to create athin layer of oxide on top of the exposed surfaces of the respectiveeSiGe regions;

FIG. 6 depicts, through a cross-sectional view, a resulting intermediatesemiconductor structure after depositing a SiN layer by LPCVD over bothNFET and PFET devices and forming thick SIN disposable spacers at bothNFET and PFET devices;

FIG. 7 depicts, through a cross-sectional view, a resulting intermediatesemiconductor structure after performing selective epitaxial Si raisedsource/drain (RSD) regions for each said NFET and PFET device; and,

FIG. 8 depicts, through a cross-sectional view, a resulting structureafter stripping the SiN disposable spacer from the CMOS structure shownin FIG. 7.

DETAILED DESCRIPTION

The present invention is directed to a method for forming ultra-thin SOI(UTSOI) field effect transistors with stressed channel regions thatprovide increased carrier mobility.

FIG. 1 shows, through cross-sectional view, a semiconductor structure 10resulting from conventional UTSOI processing. As shown, in FIG. 1, thereis first fabricated an SOI structure including a buried oxide (BOX)region 15 (e.g., an oxide, nitride, oxynitride or any combinationthereof with an oxide such as SiO₂ being most typical) that is locatedbetween a top Si-containing layer 18 and a bottom Si-containing layer12. Preferably, the BOX region 15 is continuous. The thickness of theBOX region 15 formed in the present invention may vary depending uponthe exact embodiments and conditions used in fabricating the same.Typically, however, the BOX region has a thickness from about 200 toabout 1800 Å, with a BOX thickness from about 1300 to about 1600 Å beingmore typical.

Insofar as the top Si-containing layer 18 of the SOI substrate 10 isconcerned, that Si-containing layer may have a variable thickness, whichis also dependent on the embodiment and conditions used in fabricatingthe SOI substrate. Typically, however, the top Si-containing layer 18 ofthe SOI substrate 10 has a thickness from about 10 to about 1000 Å, witha top Si-containing layer thickness from about 200 to about 700 Å beingmore typical. According to the invention, the ultra-thin SOI layer 18 isof a thickness ranging between 10 and 300 Å. The thickness of the bottomSi-containing layer 12 of the SOI substrate 10 is inconsequential to thepresent invention.

The UTSOI substrate of the present invention can be used in forminghigh-performance semiconductor devices or circuits. Examples of suchdevices or circuits that can contain the SOI substrate of the presentinvention include, but are not limited to: microprocessors, memory cellssuch as dynamic random access memory (DRAM) or static random accessmemory (SRAM), application specific integrated circuits (ASICs), opticalelectronic circuits, and larger and more complicated circuits. Sincethese devices or circuits are well known to those skilled in the art, itis not necessary to provide a detail description concerning the sameherein. It is however emphasized that the active devices and/or circuitsof such semiconductor devices and circuits are typically formed in thetop Si-containing layer of the UTSOI substrate. The invention isdescribed hereinafter with respect to forming NFET device 25 and PFETdevice 30 formed in the top Si-containing layer of the SOI substrate.

The term “Si-containing” when used in conjunction with layers 12 and 18denotes any semiconductor material that includes silicon therein.Illustrative examples of such Si-containing materials include but arenot limited to: Si, SiGe, SiGeC, SiC, Si/Si, Si/SiGe, preformed SOIwafers, silicon germanium-on-insulators (SGOI) and other likesemiconductor materials. The preformed SOI wafers and SGOI wafers, whichcan be patterned or unpatterned, may also include a single or multipleburied oxide regions formed therein. The Si-containing material can beundoped or doped (p or n-doped) depending on the future use of the SOIsubstrate.

As part of the conventional UTSOI processing, the SOI layer 18 isthinned using oxidation and wet etch techniques. After forming theultra-thin SOI layer 18, very thin pad oxidation and pad nitride layersare deposited and via lithographic techniques, the active UTSOI areas26, 31 for respective NFET device 25 and PFET transistor device 30 aredefined. That is, a lithographic mask is patterned and formed over thetop SOI layer 18 to expose regions for forming shallow trench isolation(STI) structures. This processing includes applying a photoresist to thesurface of the SOI substrate 18, exposing the photoresist and developingthe exposed photoresist using a conventional resist developer. Theetching step used in forming the STI trenches includes any standard Sidirectional reactive ion etch process. Other dry etching processes suchas plasma etching, ion beam etching and laser ablation, are alsocontemplated herein. The etch can be stopped on the top of the thick BOXlayer 15 with no more than 50 Å BOX loss. The STI regions 20 a, 20 b and20 c are then formed, e.g., by depositing an STI oxide, e.g., SiO₂ inthe formed trenches, annealing and chemical mechanical polishing (CMP)the resultant structure. These STI regions isolate the NFET 25 and PFET30 devices to be formed.

Continuing, further processing steps are performed for forming the NFET25 and PFET 30 devices including: preparing a top-contact to back Sisubstrate formation. This may be achieved, for example, by the followingsteps: (i) blanket nitride deposition, (ii) lithographically definingcontact areas on STI oxide regions, (iii) a thin nitride RIE followed bya deep oxide RIE to create a trench all the way down to the Si substrate12, (iv) resist strip, (v) thick poly silicon deposition, and (vi) polysilicon CMP that stops on the thin nitride layer, performing an STIdeglaze to strip the previously formed pad nitride and pad oxide layers(not shown) [pad nitride is stripped using hot phosphoric acid and thenpad oxide is removed using hydrofluoric acid], forming a sacrificialoxidation (sacox) layer to screen well implants for each device, andperforming an ion implantation step for forming CMOS wells by: (i)lithographically defining NFET areas 26, (ii) p-type ion implants into26, examples are Boron, BF2, or Indium, (iii) resist strip, (iv)lithographically defining PFET areas 31, (v) n-type ion implants into31, such as Arsenic, Phosphorus, or Antimony, and (vi) resist strip. TheCMOS well implant, which typically forms a well region within the SOIlayer 18, is carried out using a conventional ion implantation processwell known to those skilled in the art. P- or N-type dopants can be usedin forming the well region. For example, for the NFET, a p-well may befabricated in the active UTSOI area 26 for the NFET, an n-well may befabricated in the active UTSOI area 31 for the PFET. After ionimplantation, wafers are subjected to rapid thermal annealing to removeimplant damage. After forming CMOS NFET and PFET p-well and n-wellstructures, respectively, a step is performed for stripping thesacrificial oxidation layer. Then, a gate dielectric step is performedfor forming the respective gate dielectric layers 36, 41 for eachrespective NFET 25 and PFET 30 device.

The gate dielectric layers 36, 41 for each of the respective NFET 25 andPFET 30 devices may comprise conventional dielectric materials such asoxides, nitrides and oxynitrides of silicon that have a dielectricconstant from about 4 (i.e., typically a silicon oxide) to about 8(i.e., typically a silicon nitride), measured in vacuum. Alternatively,the gate dielectric 14 may comprise generally higher dielectric constantdielectric materials having a dielectric constant from about 8 to atleast about 100. Such higher dielectric constant dielectric materialsmay include, but are not limited to hafnium oxides, hafnium silicates,zirconium oxides, lanthanum oxides, titanium oxides,barium-strontium-titantates (BSTs) and lead-zirconate-titanates (PZTs).The gate dielectrics 36, 41 for each of the respective NFET 25 and PFET30 devices may be formed using any of several methods that areappropriate to its material of composition. Non-limiting examplesinclude thermal or plasma oxidation or nitridation methods, chemicalvapor deposition methods (including atomic layer deposition methods) andphysical vapor deposition methods. Typically, the gate dielectric layers36, 41 for each of the NFET 25 and PFET 30 devices comprise a thermalsilicon oxide dielectric material that has a thickness from about 10 toabout 30 angstroms.

Continuing, there is next formed the gate electrodes 37, 42 for eachrespective NFET 25 and PFET 30 devices. The gate electrodes 37, 42 maycomprise materials including but not limited to certain metals, metalalloys, metal nitrides and metal suicides, as well as laminates thereofand composites thereof. The gate electrodes 37, 42 may also comprisedoped polysilicon and polysilicon-germanium alloy materials (i.e.,having a dopant concentration from about 1e19 to about 1e22 dopant atomsper cubic centimeter) and polycide materials (doped polysilicon/metalsilicide stack materials). Similarly, the foregoing materials may alsobe formed using any of several methods. Non-limiting examples includesalicide methods, chemical vapor deposition methods and physical vapordeposition methods, such as, but not limited to evaporative methods andsputtering methods. Typically, the gate electrodes 37, 42 each comprisea doped polysilicon material that has a thickness from about 500 toabout 1500 angstroms. The NFET gate polysilicon is then doped withn-type dopants (As or P or Sb) and the PFET gate polysilicon with p-typedopants (B or BF₂ or In). Selective doping is achieved usingphotolithography to cover one type of FETs while exposing the other toion implants.

In a further processing step, capping layers 38, 43 for respective gatedevices 25 and 30 are formed that comprises a capping material that inturn typically comprises a hard mask material. This hard mask materialis required for selective Si or SiGe epitaxy that is performed later.Without the hard mask, Si or SiGe also gets deposited on the gatepolysilicon and causes a gate mushroom that could come in physicalcontact with the raised source/drain, thereby, causing gate-to-sourceand/or gate-to-drain shorts. Dielectric hard mask materials are mostcommon but by no means limit the instant embodiment or the invention.Non-limiting examples of hard mask materials include oxides, nitridesand oxynitrides of silicon. Oxides, nitrides and oxynitrides of otherelements are not excluded. The capping material may be formed using anyof several methods that are conventional in the semiconductorfabrication art. Non-limiting examples include chemical vapor depositionmethods and physical vapor deposition methods. Preferably, a siliconnitride (SiN) and high-temperature oxide (HTO) hard mask deposition isperformed to cap the gate polysilicon for raised source/drain (RSD)integration. Using typical gate lithography and etch techniques, thegate devices 25 and 30 result having a respective SiN cap 38, 43 formedon top. These respective SiN capping layers 38, 43 have a thickness fromabout 100 to about 500 angstroms.

In a further processing step such as shown in FIG. 1, each of therespective gate devices 25 and 30 are re-oxidized (ReOx) such that athin layer of dielectric material, e.g., an oxide, is formed to covereach gate electrode structure. Thus, as shown in FIG. 1, NFET 25includes a thin layer 39 of oxide, while PFET 30 includes a thin layer44 of oxide. There is no re-oxide material layers 39 and 44 on therespective top cap layers 38, 43 as shown in FIG. 1 because only exposedSi or polysilicon is oxidized while nitride is not.

The CMOS structure at this stage is shown in FIG. 1. Continuing to FIG.2, there is shown the resultant structure after blanket depositing athin conformal layer 40 of SiN material by low-pressure chemical vapordeposition (LPCVD) over each of the respective devices 25, 30. In oneembodiment, the thin conformal layer 40 of SiN material may range up toabout 10 nm in thickness. As part of this process, thin disposablespacers are formed on each sidewall of the gate electrodes. For example,this step results in spacers 38 a, 38 b formed on NFET device 25 inaddition to the thin conformal layer 40 of SiN material formed above theReOx layer 39. In a further processing step, only the NFET device 25 iscovered with a resist material and a SiN reactive ion etch (RIE) isperformed on the PFET device 30 to form the thin disposable spacers 43a, 43 b on PFET device 30. As a result of the etch, the thin conformalthin conformal layer 40 of SiN material is removed form atop the ReOxlayer 44 at the PFET device 30. The CMOS structure resulting at thisstage is shown in FIG. 2.

Continuing to FIG. 3, there is shown the resultant structure aftercreating a recess 50 at the PFET device. That is, as shown in FIG. 3,with the NFET 25 now covered with blanket SiN, a recess is created inthe Si active region at the PFET device 30 by removing portions of theSOI layer 31. This may entail pre-cleaning the PFET structure using anhydrofluoric acid (HF) wet etch or RIE chemical oxide removal (COR) dryetch to remove the exposed top ReOx layer 44, applying a furnaceoxidation step to consume the underlying Si of the SO layer 31, and thenremoving the oxide removal using HF wet etch or RIE COR dry etch. Theresultant CMOS structure at this stage is shown in FIG. 3 showing theshort SOI channel region 31′ underlying the gate oxide of the PFET 30.

Continuing to FIG. 4, with the recessed Si structure 50 at the PFETdevice 30, a selective epitaxial SiGe growth process is performed at thePFET to create the resulting CMOS structure shown in FIG. 4. In thestructure shown in FIG. 4, epitaxially grown SiGe extensions 60 a, 60 bcorresponding drain and source regions are formed for the PFET device30. The epitaxial method that may be used for forming the embedded SiGe(eSiGe) extensions 60 a, 60 b in PFET device may use source materialsand deposition conditions that are otherwise generally conventional inthe semiconductor fabrication art. Preferably, the eSiGe extensions 60a, 60 b are formed a few nanometer higher than the short SOI channelregion 31′ thus maximizing its compressive stress effect.

Continuing to FIG. 5, an oxidation step is performed to create a thinlayer of oxide 70 a, 70 b on top of the exposed surfaces of therespective eSiGe regions 60 a, 60 b to create the intermediate CMOSstructure shown in FIG. 5. This thin layer of oxide is deposited usingconventional deposition techniques such as low-temperature CVD to athickness ranging between 30 and 100 angstroms. This thin layer of oxidewill act as the RIE stop layer for SiN RIE in a subsequent step nowdescribed herein with respect to FIG. 6.

FIG. 6 depicts the resultant structure formed after depositing a SiNlayer by LPCVD over both NFET 25 and PFET 30 devices. In one embodiment,the SiN layer is deposited to a thickness ranging from between 30-40 nmthick as this is an optimum range for best ac-performance. That is, ifthe RSD is too close to the gate, one pays a parasitic capacitancepenalty and if the RSD is too far, then one pay a large parasiticresistance penalty. Further, a SiN RIE step is performed to form thickSiN disposable spacers 80 at both NFET 25 and PFET 30 devices as shownin FIG. 6.

Continuing to FIG. 7, with the thick disposable spacers 80 at both NFETand PFET devices, a selective epitaxial Si raised source/drain (RSD)growth step is performed to create the CMOS structure shown in FIG. 7.As shown in FIG. 7, the raised source/drain (RSD) growth step results inraised source/drain (RSD) structures 85 a, 85 b of about 100 to 400angstroms in thickness for NFET device 25 and raised source/drain (RSD)structures 90 a, 90 b of about 100 to 400 angstroms in thickness forPFET device 30. Each of the formed RSD structures 85 a, 85 b and 90 a,90 b are distanced from the polysilicon gate edge by 30-40 nm distancecorresponding to the thickness of the SiN disposable spacers 80. Thisdistance between each formed RSD structure and a respective gate edge issufficient to lower parasitic capacitance between the gate and therespective source/drain.

Referring to FIG. 8, the SiN disposable spacer 80 is stripped from theCMOS structure shown in FIG. 7 using hot phosphoric acid or likeselective etching material.

From this structure, conventional CMOS processing may continue to finishCMOS FEOL processing including steps such as: halo ion implantation,offset spacer formation, extension ion implantation, final spacerformation, deep S/D ion implantation, deep S/D activation anneals,silicidation, and dual stress liner (DSL) process.

The present invention thus provides a novel semiconductor devicestructure that includes integrating PFET devices with an embedded SiGeextension coupled with raised CMOS source drain regions. The embeddedSiGe extensions particularly help to 1) create compressive stress in thethin SOT layer thereby improving hole mobility (the eSiGe extensions arepositioned close to the channel region thereby maximizing its stresseffect); 2) minimize dopant (e.g., Boron) loss in extension regions,thereby enhancing extension conductivity; and, 3) for relatively thickSOI or bulk PFETS, the presence of the Ge retards boron diffusion thusenabling a shallow extension junction which is beneficial toshort-channel control.

While there has been shown and described what is considered to bepreferred embodiments of the invention, it will, of course, beunderstood that various modifications and changes in form or detailcould readily be made without departing from the spirit of theinvention. It is therefore intended that the invention be not limited tothe exact forms described and illustrated, but should be constructed tocover all modifications that may fall within the scope of the appendedclaims.

1. A semiconductor transistor device comprising: a semiconductorsubstrate having a buried layer of insulator material formed therein andan Ultra-thin Silicon On Insulator (UTSOI) layer formed a top saidburied layer of insulator material; STI (Shallow Trench Isolation)structures formed in said UTSOI layer for isolating active areas forforming an NFET device and PFET for forming a gate channel region forrespective NFET and PFET device; a gate structure including a gatedielectric layer formed in each isolated active area for each respectiveNFET and PFET device and a gate electrode conductor formed atop eachsaid respective gate dielectric layer for each respective NFET and PFETdevice; epitaxially grown embedded semiconductor extensions formed inrespective recesses created as a result of removing portions of the SOIlayer at respective source region and drain region at each side of saidgate electrode of said PFET device; raised source/drain (RSD) structureson top of respective epitaxially grown embedded semiconductor extensionscorresponding to said source and drain regions of the PFET device; and,raised source/drain (RSD) structures on top of source and drain regionsof the NFET device, wherein said epitaxially grown embeddedsemiconductor extensions create compressive stress in the UTSOI layerthereby enhancing PFET device performance.
 2. The semiconductortransistor device as claimed in claim 1, wherein said formed eSiGeextensions abut the short SOI channel region to maximize its compressivestress effect.
 3. The semiconductor transistor device as claimed inclaim 1, wherein said formed epitaxial raised source/drain (RSD)structures range between 100 to 400 angstroms in thickness for said PFETdevice.
 4. The semiconductor transistor device as claimed in claim 1,wherein, for each formed NFET and PFET device, each said formedepitaxial RSD structures are located a distance from an edge of arespective gate conductor that is sufficient to lower parasiticcapacitance between the gate and the respective source/drain structurefor each formed NFET and PFET device.
 5. The semiconductor transistordevice as claimed in claim 1, wherein said distance between between eachformed RSD structure and a respective gate edge is between 30 nm-40 nm.6. A semiconductor transistor device comprising: a semiconductorsubstrate having a buried layer of insulator material formed therein andan Ultra-thin Silicon On Insulator (UTSOI) layer formed a top saidburied layer of insulator material, said UTSOI layer providing an activearea for a PFET device; a gate structure including a gate dielectriclayer formed in said UTSOI active area for said PFET device and a gateelectrode conductor formed atop said gate dielectric layer; epitaxiallygrown embedded semiconductor extensions formed in respective recessescreated as a result of removing portions of the UTSOI layer atrespective source region and drain region at each side of said gatestructure of said PFET device; and, raised source/drain (RSD) structureson top of respective epitaxially grown embedded semiconductorextensions, wherein said epitaxially grown embedded semiconductor PFETextensions create compressive stress in the UTSOI layer therebyenhancing PFET device performance.